Many applications in modern electronics require that continuous-time signals be converted to discrete signals for processing using digital computers and signal processors. Conventionally, this transformation is made using a method similar to converter circuit 5, illustrated in FIG. 1. Circuit 5 converts analog input 6 (i.e., both continuous in time and continuously variable) to discrete digital output 16 (i.e., both sampled in time and quantized in value) using lowpass filter 8, sample-and-hold circuit 10 (sampler), and quantizer 14. The instantaneous bandwidth of such a sampled system is limited by the Nyquist criterion to a maximum theoretical value equal to one-half the sample clock (fCLK) frequency (i.e., the Nyquist limit). Therefore, the purpose of lowpass filter 8, in circuit 5, is to reject frequencies above the Nyquist limit, so that discrete output 16 is not corrupted by errors related to aliasing. For this reason, filter 8 is often referred to in the prior art as an anti-aliasing filter. At intervals determined by clock frequency 12, sample-and-hold circuit 10 captures the output value of anti-aliasing filter 8 (i.e., an analog signal), and holds that value while quantizer 14 produces, using a rounding operation, a discrete-time, discretely-valued output 16 (i.e., a digital signal). The number of discrete levels in the rounding operation of quantizer 14 determines the conversion resolution, or maximum precision, associated with analog-to-digital converter circuit 5. Converter precision is often specified as an effective number of bits (ENOB), such that for Q levels in the rounding operation, the ENOB is less than or equal to log2(Q).
In general, the precision of an analog-to-digital converter (ADC) is less than log2(Q) because of impairments such as sampling uncertainty, or timing jitter, that degrade the accuracy of the sampling/quantization operation and reduce the quality of the conversion process. Although one source of sampling uncertainty is the inability of sample-and-hold circuit 10 to consistently capture signals on the transitions (i.e., rising and falling edges) of sample clock 12, a primary source of sampling jitter/uncertainty in conventional ADCs tends to be the sample clock source itself. The sample clock is produced by a circuit, often called an oscillator, which conventionally includes a network that is resonant at a particular frequency (i.e., a resonator). FIG. 2A is an exemplary conventional oscillator known as a Pierce oscillator. Sampling jitter/uncertainty results when the oscillator output frequency varies or drifts over time due to resonator instabilities, and/or other circuit imperfections. Fluctuations in oscillator output frequency and/or phase are generally classified according to the time scale over which the fluctuations occur. For example, rapid fluctuations in oscillator output frequency, such as those having periods on the order of nanoseconds to microseconds, are referred to as short-term jitter, or high-frequency jitter (i.e., white phase noise). Conversely, slow fluctuations in oscillator output frequency, such as those having periods on the order of milliseconds to tenths of seconds, are referred to as long-term jitter or low-frequency jitter (i.e., flicker-phase noise or white-frequency noise). Finally, extremely slow fluctuations in oscillator output frequency, such as those with periods on the order of seconds to many seconds, are referred to as wander (i.e., flicker-frequency noise or random frequency walk). FIG. 2B provides a classification of clock frequency instability based on the rate of variation exhibited by the fluctuations in the oscillator output. As shown in FIG. 2B, low-frequency jitter and wander typically have greater magnitudes than high-frequency jitter.
To illustrate the effects of sampling jitter on an ADC, it is informative to consider first the case of a narrowband (sinusoidal) input signal, such as x(t)=Am·sin(ωmt+φm), with arbitrary amplitude (Am), arbitrary phase (φm), and angular frequency ωm<½·fCLK. Assuming infinite resolution (i.e., number of rounding levels Q→∞), the discrete-time output of the converter is given byŷk(n)=Am sin(ωmT·n+φm+ωm·φ),where the sampling interval T=1/fCLK and φ is a white, Gaussian noise sequence produced by sampling jitter (uncertainty) having power σφ2 and power spectral density N0 (i.e., N0=σφ2/½·fCLK)). For the case where |φ|<<1, which is typical for high-precision clock sources, it is relatively straightforward for those skilled in the art to show thatŷn(n)≈Am·sin(ωmT·n+φm+Am·cos(ωmT·n+φm)·(ωm·φ),where the first term in the above equation is the sampled input signal and the second term is noise introduced by sampling jitter. The power in the noise term increases with the square of the input angular frequency ωm according to PNoise=½·Am2·σφ2·ωm2, and this noise adds directly to the converter output to degrade conversion accuracy. Specifically, the effective resolution (i.e., ENOB) of a data converter degrades by 0.5 bits for every factor of two increase in output noise.
The jitter analysis above can be extended to the case of a broadband input signal by considering that any real, bandlimited signal can be approximated by a finite sum of sinusoids via a Fourier series. In analyzing the effects of sampling jitter, therefore, it is convenient to represent a broadband input signal (x), with bandwidth fB, as the sum of K sinusoids having arbitrary amplitude and arbitrary phase, where
            x      ⁡              (        t        )              =                  ∑                  k          =          0                          K          -          1                    ⁢                        A          k                ·                  sin          ⁡                      (                                                            ω                  k                                ⁢                t                            +                              ϕ                k                                      )                                ,amplitude values Ak are uniformly distributed over the interval [−1, 1], phase values φk are uniformly distributed over the interval (−π, +π, and angular frequency values ωk are uniformly distributed over the interval [0, 2π·fB] (i.e., ω0=0 and ωK-1=2π·fB). Again assuming infinite resolution (i.e., number of rounding levels Q→∞), the discrete-time output of the converter is given by
                                                        y              ^                        k                    ⁡                      (            n            )                          =                ⁢                              ∑                          k              =              0                                      K              -              1                                ⁢                                    A              k                        ⁢                          sin              ⁡                              (                                                                            ω                      k                                        ⁢                                          T                      ·                      n                                                        +                                      ϕ                    k                                    +                                                            ω                      k                                        ·                    φ                                                  )                                                                            ≈                ⁢                                            ∑                              k                =                0                                            K                -                1                                      ⁢                                          A                k                            ·                              sin                ⁡                                  (                                                                                    ω                        k                                            ⁢                                              T                        ·                        n                                                              +                                          ϕ                      k                                                        )                                                              +                                                ⁢                              ∑                          k              =              0                                      K              -              1                                ⁢                                    A              k                        ·                          cos              ⁡                              (                                                                            ω                      k                                        ⁢                                          T                      ·                      n                                                        +                                      ϕ                    k                                                  )                                      ·                          (                                                ω                  k                                ·                φ                            )                                          where the second term, which is the output noise introduced by sampling jitter, has
      P    noise    =                    1        2            ·      K      ·      E        ⁢                  {                  A          k          2                }            ·              σ        φ        2            ·              1        K            ·                        ∑                      k            =            0                                K            -            1                          ⁢                              ω            k            2                    .                    powerAs K→∞ the power in the noise term converges to
            P      noise        =                  1        3            ·              σ        S        2            ·              σ        φ        2            ·                        (                      2            ⁢                                                  ⁢                          π              ·                              f                B                                              )                2              ,where σS2 is the input signal power. Therefore, the extent to which sampling jitter degrades conversion accuracy is proportional to the square of the input signal bandwidth fB.
As a result of the above analysis, the present inventor has indentified a need for minimizing the effects of sampling jitter in data converter circuits, particularly those that are required to process input signals with high-frequency content (i.e., large ωk), or wide bandwidth (i.e., large fB). To overcome the processing speed limitations of electronic circuits, high-frequency converters conventionally employ an arrangement where multiple, distinct converters are operated in parallel (i.e., parallel processing). Conventional parallel processing arrangements include time-interleaving (time-slicing) converters and frequency-interleaving (frequency-slicing) converters. For interleaving in time, a high-speed sample clock is decomposed into lower-speed sample clocks at different phases. Each converter in the time-interleaving array is clocked with a different clock phase, such that the conversion operation is distributed in time across multiple converters (i.e., polyphase decomposition). While converter #1 is processing the first sample, converter #2 is processing the next sample, and so on.
For interleaving in frequency, the total bandwidth of the continuous-time signal is uniformly decomposed (i.e., divided) into multiple, narrowband segments (i.e., sub-bands). Each parallel processing branch converts one narrowband segment, and all the converter processing branches operate from a single, common sampling clock. According to one representative implementation of a frequency-interleaving ADC 30A, shown in FIG. 3A, the individual bands are separated out and downconverted to baseband. More specifically, the input signal 31 is provided to a set of multipliers 32A together with the band's central frequencies 33A-35A. The resulting baseband signals are then provided to identical, lowpass filters 36A that are designed to spectrally decompose the input signal (i.e., signal analysis), in addition to minimizing aliasing. Each such filtered baseband signal is then digitized by sampling/quantization circuit 40A, digitally upconverted by multipliers 42A, using digitized sinusoids 43A-45A (or alternatively simply upsampled), and then bandpass filtered (i.e., within reconstruction filters 46-48) in order to restore the input signal to its previous frequency band (i.e., signal synthesis). Finally, the individual bands are recombined in one or more adders 49. Instead of operating at a sampling frequency equal to twice the bandwidth of the input signal, each converter 40A in the interleaved array is able to operate at a lower sampling frequency equal to twice the bandwidth of each subdivided, downcoverted band (i.e., the portion of the input signal intended to be converted by the respective processing branch).
Frequency-interleaving converter circuit 30A, illustrated in FIG. 3A, is typically referred to as a frequency-translating hybrid (FTH) architecture. See Mazlouman, S., “Digital Compensation Techniques for Frequency-Translating Hybrid Analog-to-Digital Converters”, IEEE Transactions on Instrumentation and Measurement, Volume 60, Number 3, 2011. An alternative, conventional frequency-interleaving converter, first described by Petraglia and Mitra in 1990, is the hybrid filter bank (HFB) converter circuit 30B, shown in FIG. 3B. See Petraglia, A., “High Speed A/D Conversion using QMF Filter Banks”, Proceedings: IEEE International Symposium on Circuits and Systems, 1990. The operation of the HFB converter is similar to that of the FTH converter, except that the input signal 31 is provided to a set of analog, bandpass filters 36B-38B (i.e., conventionally referred to as analysis filters) for spectral decomposition, before being provided to multipliers 32B for downconversion to baseband using the band's central frequencies 33B-35B. The analog input (bandpass-decomposition) filters are conventionally designed for minimum spectral overlap (i.e., non-overlapping passbands), with preferred bandwidths of fCLK/2M, where fCLK is the converter sample-rate frequency and M is the number of parallel processing branches. See Velazquez, S., “Design of Hybrid Filter Banks for Analog/Digital Conversion”, IEEE Transactions on Signal Processing, Volume 46, Number 4, 1998. As in the FTH approach, each converter 40B in the interleaved array of the HFB converter operates at a sampling frequency equal to twice the bandwidth of each subdivided, downcoverted band (i.e., the portion of the input signal intended to be converted by the respective processing branch). Conventionally, the FTH approach is preferred over the HFB approach because: 1) matched lowpass-decomposition filters are easier to implement than matched bandpass-decomposition filters, 2) filtering after downconversion ensures minimal spectral overlap between sub-bands; and 3) filtering prior to digitizing reduces errors due to aliasing. See Ding, G., “Frequency-Interleaving Technique for High-Speed A/D Conversion”, Proceedings: IEEE International Symposium on Circuits and Systems, 2003. The present inventor has discovered, however, that since the FTH approach employs no bandlimiting prior to the downconversion operation, intermodulation distortion that is introduced by the input multipliers can degrade conversion accuracy.
A variation on the conventional hybrid filter bank (HFB) converter is the multiband delta-sigma (MBΔΣ) converter circuit 30C, shown in FIG. 3C. See Aziz, P., “Multi Band Sigma Delta Analog to Digital Conversion”, IEEE International Conference on Acoustics, Speech, and Signal Processing, 1994. This approach attempts to solve the difficulties associated with implementing matched bandpass-decomposition (analysis) filters by eliminating them completely. And unlike conventional FTH and HFB converters, the MBAΔΣ converter performs no spectral (frequency) decomposition in the analog domain. The input signal 31 instead is provided directly to the sampling/quantization elements 40C, which consequently prevent aliasing errors by sampling at twice the bandwidth of the input signal, rather than at twice the bandwidth of a subdivided band. The present inventor has discovered that a primary disadvantage of MBAΔΣ approach is increased sensitivity to timing jitter, due to the presence of wideband signals at the inputs of each sampling/quantization circuit (i.e., no analog bandlimiting prior to sampling and quantization). The present inventor also has discovered that another disadvantage of frequency decomposition in the analog domain is that the practical (e.g., manufacturing) constraints associated with analog bandpass filter quality factor (i.e., quality factor Q, defined as the ratio of filter center frequency to filter bandwidth) limits the number of processing branches to about 25-30, a number which may be insufficient for realizing desired bandwidth and conversion-accuracy targets.
Although, conventionally, frequency-interleaving converters are considered to be less sensitive to timing jitter than time-interleaving converters, as a result of downconversion to baseband and use of a common sampling clock (Ding 2003), timing jitter is a problem for any converter that processes high-frequency input signals. Conventional methods for reducing timing jitter generally attempt to attenuate the short-term jitter (i.e., white phase noise) of the sampling clock source, ignoring longer-term jitter and drift. See Smilkstein, T., “Jitter Reduction on High-Speed Clock Signals” (PhD Thesis), University of California, Berkeley, 2007. These conventional methods typically involve improving the stability of the clock oscillator itself, for example using high-precision atomic or quartz resonators, or involve use of phase-locked loop (PLL) techniques (Smilkstein, 2007) to slave the frequency of a relatively stable oscillator (i.e., atomic or quartz) to the average frequency of a relatively unstable or noise-corrupted clock source.
Circuit 50, illustrated in FIG. 4A, is an exemplary PLL of the type conventionally used for reducing the high-frequency timing jitter of a sampling clock source. In circuit 50, the output phase of a clock source 52, which has been corrupted by noise, is compared to the output phase of a low-jitter, controlled oscillator 60 within phase detector 56. The phase difference 57 (i.e., phase error) between the noisy (high-jitter) clock source and the precision oscillator is lowpass filtered, by loop filter 58, to produce a control signal 59. Control signal 59 adjusts the frequency of controlled oscillator 60 to match the average frequency of noisy clock source 52. A frequency divider 62 can be included in the feedback path of the PLL such that the frequency (fOSC) at PLL output 61 equals fOSC=D·f0, where f0 is the nominal frequency of the noisy clock source and D is the frequency-output to frequency-input ratio of the divider.
The jitter transfer function of circuit 50 is the frequency response from the output 53 of noisy oscillator 52, to the output 61 of the PLL. For a phase detector 56 with gain KD, a controlled oscillator 60 with gain KV, and a loop filter 58 with second-order, lag-lead response
            H      ⁡              (        s        )              =                  1        +                  β          ·          s                            α        ·        s              ,the jitter transfer function, HJTF, has a lowpass response given by
            H      JTF        =                  ω        n        2                    1        +                  2          ⁢                      ζω            n                          +                  ω          n          2                      ,where the PLL natural frequency ωn=√{square root over (KD·KV/α)} and the PLL damping factor
  ζ  =            1      2        ·          ω      n        ·          β      .      For reference, the jitter transfer function for PLL circuit 50 is plotted in FIG. 4B. As illustrated in FIG. 4B, jitter that fluctuates at a rate greater than ωn is attenuated by the PLL. The clock signal at the output of the PLL will be more stable than the output of noisy clock source 52, when: (1) controlled oscillator 60 has very low jitter (i.e., the output of oscillator 60 is relatively stable) and (2) ωn is lower than the fluctuation rate (frequency) for the dominant source(s) of jitter (e.g., white frequency, flicker phase, white phase).
The conventional jitter attenuation methods, based on PLLs with high-stability controlled oscillators, can be useful for reducing the high-frequency jitter (i.e., short-term jitter) of a noise-corrupted clock source, as illustrated by the exemplary jitter transfer function in FIG. 4B. In practice, however, the present inventor has discovered that conventional, PLL-based jitter attenuation methods have several disadvantages that limit their utility in converter applications, including: (1) a tunable, high-precision oscillator generally cannot accommodate the wide range of conversion rates at which a converter typically needs to operate; (2) overall timing jitter is not reduced significantly because timing jitter tends to be dominated by low-frequency jitter as illustrated in FIG. 2B (i.e., low-frequency jitter has higher magnitude than high-frequency jitter); and (3) the cost and complexity may be prohibitive because the high-precision resonators needed to implement the controlled clock source cannot be integrated onto silicon devices using conventional methods. For these reasons, improved apparatuses and methods are needed for reducing the performance degradation caused by timing jitter, particularly in converter applications where high-frequency input signals are processed.